Car Solutions QPI-G7-MAIN-V2.0 Bedienungsanleitung PDF herunterladen (Seite 61)

MT9V125_DS Rev. U 3/15 EN 61 ©Semiconductor Components Industries, LLC,2005.

MT9V125: SOC VGA Digital Image Sensor

Appendix A: Serial Bus Description

Two-Wire Serial Bus Timing

The two-wire serial interface operation requires a certain minimum of master clock

cycles between transitions. These are specified below in master clock cycles.

Figure 40: Serial Host Clock Period and Duty Cycle

Figure 41: Serial Host Interface Start Condition Timing

Figure 42: Serial Host Interface Stop Condition Timing

Notes: 1. All timing are in units of master clock cycle.

Figure 43: Serial Host Interface Data Timing for Write

Notes: 1. SDATA is driven by an off-chip transmitter.

SCLK

< 400 KHz Max

SCLK

SDATA

SCLK

DATA

SCLK

DATA

1 2 ... 56 57 58 59 60 61 62 63 64 65 66 67 68 69

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