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MT9V125_DS Rev. U 3/15 EN 20 ©Semiconductor Components Industries, LLC,2005.
MT9V125: SOC VGA Digital Image Sensor
Detailed Architecture Overview
Notes: 1. See “Register Notation” on page 4 of the register rerference for a description of the register nota-
tion.
2. R21:1[0]
3. R19:1[7]
4. R19:1[1:0]
5. R155:1[12]
6. R155:1[8]
7. R155:1[7:6]
Table 5 identifies the readout format, output format, and output ports supported by the
MT9V125. This table gives output formats supported by the MT9V125. The “DevWare
Video Output Mode” column identifies the name used by the ON Semiconductor
DevWare demonstration program to execute the readout mode. MT9V125 registers that
enable these modes are specified in Table 6 on page 21.
Table 4: Readout Mode Register Settings – D
OUT Not Qualified
When DOUT is not qualified with FV and LV
Readout Format/
Output Format/
Output Port
1
NTSC or
PAL
2
Hold FV
HIGH
3
Output
Select
MUX
4
Sensor
Stand-
Alone
Mode
5
Enable
RGB
6
RGB
Output
Format
7
Output Odd
Field
Resolution
Output Even
Field
Resolution
Readout
Format/
Output
Frame
Resolution
Interlaced/
CCIR656/
D
OUT[7:0] &
LVDS
0: NTSC00000720x244720x243720x487
Interlaced/
CCIR656/
D
OUT[7:0] &
LVDS
1: PAL00000720x288720x288720x576
Table 5: MT9V125 Readout Modes
Readout Format–Output Format Parallel DOUT
Composite Analog
Out LVDS Devware Video Output Mode
Interlaced–CCIR656 Supported Supported Supported Interlaced/CCIR656
Interlaced–RGB Supported Not supported Not supported Interlaced/RGB
Interlaced–Raw Bayer Supported Not supported Not supported Interlaced/Raw Bayer
Progressive–Raw Paired Bayer Supported Not supported Not supported Progressive/Raw Paired Bayer
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